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fedl7033-04 issue date: oct. 13, 2011 ml7033 dual-channel line card codec 1/52 general description the ml7033 is a 2-channel pcm codec cmos ic designed for central office (co) and customer premise equipment (cpe) environments. the ml7033 device contains 2-channel analog-to-digital (a/d) and digital-to-analog (d/a) converters with multiplexed pcm input and output. the ml7033 is designed for single-rail, low power applications. the high integration of the ml7033 reduces the number of external components and overall board size. the ml7033 is best suited for line card applications and provides an easy interface to subscriber line interface circuits (slic?s), in particul ar the intersil rslic tm series. features ? seamlessly interfaces with intersil rslic tm series devices ? single 5 volt power supply (4.75 v to 5.25 v) ? ? - ? adc and dac ? pcm format: -law/a-law (itu-t g.711 compliant), 14-bit linear (2?s complement) ? optional wideband filter for v.90 data modem applications ? low power consumption - 2-channel operating mode: 115 mw (typical) 180 mw (max) - 1-channel operating mode: 80 mw (typical) 115 mw (max) - power-down mode: 0.1 mw (typical) 0.25 mw (max); pdn pin = logic ?0? ? power-on reset ? dual programmable tone generators (300 hz to 3400 hz; 10 hz intervals; 0.1 db intervals) - call progress tone, dtmf tone ? ringing tone generator (15 hz to 50 hz; 1hz intervals; 0.1 db intervals) ? pulse metering tone generator (12 khz, 16 khz; gain level selectable) ? call id tone generator (itu-t v.23, bell 202) ? analog and digital loop back test modes ? time-slot assignment ? serial mcu interface ? master clock: 2.048 mhz/4.096 mhz selectable ? serial pcm transmission data rate: 256 kbps to 4096 kbps ? adjustable transmit/receive gain (1 db intervals) ? built-in reference voltage generator ? differential or single-ended analog output selectable ? package: 64-pin plastic qfp (qfp64-p-1414-0.80-bk) (ordering part number: ml7033ga)
fedl7033-04 ml7033 2/52 block diagram rc lpf rc lpf ? - ? ad conv bpf bpf ? - ? ad conv ain2n ain2p gsx2 ain1n ain1p gsx1 p cmosy tcont xsync pcmout compressor compressor pulse meter gen.2 tout1 tout2 aout1n rc lpf rc lpf ? - ? d a conv ? - ? d a conv pulse meter gen.1 ch1tg2 cr9 b7-b1 cr7 b4-b1 cr7 b6 cr14 b6 cr14 b5 cr7 b5 cr18 b7, b6 cr18 b5, b4 cr2 b2-b1 cr2 b6-b5 cr12 b3-b0 cr5 b3-b0 cr2 b0 sg gen. sgc v ddd v dd a ag dg f2_1 f1_1 f0_1 e0_1 s wc1 bsel1 d et 1 a lm1 f2_2 f1_2 f0_2 e0_2 s wc2 bsel2 d et 2 a lm2 aout2p aout1p lpf rc lpf rc lpf ? - ? d a conv ? - ? d a conv lpf rcont rsync pcmin mcu control & clock gen. p dn r ese t mck test cidata1 cidata2 dio d e n exck i nt expander expander bclk aout2n sg cr5 b7-b4 cr12 b7-b4 cr2 b4 cr18 b7- b4, b0 ch2tg2 cr16 b7-b1 cr14 b4-b1 cr14-b7 cr7-b7 call-id2 ringtone2 ch2tg1 call-id1 ringtone1 ch1tg1 cr1 b0 cr1 b6 cr11-b3 cr1 b1 cr1 b 7 cr11-b7 slic control
fedl7033-04 ml7033 3/52 pin configuration (top view) n.c ain1n gsx1 aout1p aout1n tout1 ag sg sgc ag tout2 aout2n aout2p gsx2 ain2n n.c n.c r eset rsync xsync pcmout p cmosy pcmin dg bclk mck v ddd dio d en exck i n t n.c n.c a in1p v dda v ddd s wc 1 f2_1 f1_1 f0_1 e0_1 d et 1 a lm 1 bsel1 dg test p dn n.c n.c ain2p v dda v ddd bsel2 alm 2 det 2 e0_2 f0_2 f1_2 f2_2 swc 2 dg cidata1 cidata2 n.c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 64-pin plastic qfp
fedl7033-04 ml7033 4/52 pin descriptions pin symbol type description 1 n.c ? (leave unconnected) 2 ain1n i ch1 transmit op-amp input negative 3 gsx1 o ch1 transmit op-amp output 4 aout1p o ch1 receive output positive 5 aout1n o ch1 receive output negative 6 tout1 o ch1 tone output 7 ag ? analog ground 8 sg o signal ground for external circuit 9 sgc o signal ground for internal circuit 10 ag ? analog ground 11 tout2 o ch2 tone output 12 aout2n o ch2 receive output negative 13 aout2p o ch2 receive output positive 14 gsx2 o ch2 transmit op-amp output 15 ain2n i ch2 transmit op-amp input negative 16 n.c ? (leave unconnected) 17 n.c ? (leave unconnected) 18 ain2p i ch2 transmit op-amp input positive 19 v dda ? power supply for internal analog circuit 20 v ddd ? power supply for internal digital circuit 21 bsel2 o output for sl ic2 battery select 22 alm2 i input from slic2 thermal shut down alarm detector 23 det2 i input from slic2 switch hook, ground key or ring trip detector 24 e0_2 o output for slic2 detector mode selection 25 f0_2 o mode control output to slic2 f0 26 f1_2 o mode control output to slic2 f1 27 f2_2 o mode control output to slic2 f2 28 swc2 o output for slic2 unco mmitted switch control 29 dg ? digital ground 30 cidata1 i call id data input for ch1 31 cidata2 i call id data input for ch2 32 n.c ? (leave unconnected) 33 n.c ? (leave unconnected) 34 int o interrupt output (from slic status) 35 exck i mcu interface data clock input 36 den i mcu interface data enable input 37 dio i/o mcu interface c ontrol data input/output
fedl7033-04 ml7033 5/52 pin symbol type description 38 v ddd ? power supply for internal digital circuit 39 mck i master clock (2.048/4.096 mhz) 40 bclk i pcm data shift clock 41 dg ? digital ground 42 pcmin i pcm data input 43 pcmosy o pcm data output indicato r for time-slot assignment 44 pcmout o pcm data output 45 xsync i transmit synchronizing clock input 46 rsync i receive synchronizing clock input 47 reset i reset for control register 48 n.c ? (leave unconnected) 49 n.c ? (leave unconnected) 50 pdn i power-down control 51 test i lsi manufacturer?s test input (keep logic ?0?) 52 dg ? digital ground 53 bsel1 o output for sl ic1 battery select 54 alm1 i input from slic1 thermal shut down alarm detector 55 det1 i input from slic1 switch hook, ground key or ring trip detector 56 e0_1 o output for slic1 detector mode selection 57 f0_1 o mode control output to slic1 f0 58 f1_1 o mode control output to slic1 f1 59 f2_1 o mode control output to slic1 f2 60 swc1 o output for slic1 unco mmitted switch control 61 v ddd ? power supply for internal digital circuit 62 v dda ? power supply for internal analog circuit 63 ain1p i ch1 transmit op-amp input positive 64 n.c ? (leave unconnected) note: in this datasheet, ?1? and ?2? in names for pi ns which respectively exist for ch1 and ch2 are often substituted by ?n? (in a small letter). ex) gsx1, gsx2 ? gsxn aout1n, aout2n ? aoutnn det1 , det2 ? detn
fedl7033-04 ml7033 6/52 control register assignment address data register a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r/w cr0 0 0 0 0 0 filter2 sel filter1 sel mck sel short lin alaw mode1 mode0 r/w cr1 0 0 0 0 1 ch2tg on ch1tg on cid fmt cid ch2on cid ch1on r/w cr2 0 0 0 1 0 pmg2 frq pmg2 lv1 pmg2 lv0 pmg2 tout2 pmg1 frq pmg1 lv1 pmg1 lv0 pmg1 tout1 r/w cr3 0 0 0 1 1 tsae tsac tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 w cr4 0 0 1 0 0 det2 tim3 det2 tim2 det2 tim1 det2 tim0 det1 tim3 det1 tim2 det1 tim1 det1 tim0 r/w cr5 0 0 1 0 1 lv1r3 lv1r2 lv1r1 lv1r0 lv1x3 lv1x2 lv1x1 lv1x0 r/w cr6 0 0 1 1 0 f2_1 f1_1 f0_1 swc1 bsel1 e0_1 det1* alm1* r/w cr7 0 0 1 1 1 aout1 sel ch1tg2 tx ch1tg2 tout1 ch1tg2 lv3 ch1tg2 lv2 ch1tg2 lv1 ch1tg2 lv0 ch1tg2 _8 r/w cr8 0 1 0 0 0 ch1tg2 _7 ch1tg2 _6 ch1tg2 _5 ch1tg2 _4 ch1tg2 _3 ch1tg2 _2 ch1tg2 _1 ch1tg2 _0 r/w cr9 0 1 0 0 1 ch1tg1 lv6 ch1tg1 lv5 ch1tg1 lv4 ch1tg1 lv3 ch1tg1 lv2 ch1tg1 lv1 ch1tg1 lv0 ch1tg1 _8 r/w cr10 0 1 0 1 0 ch1tg1 _7 ch1tg1 _6 ch1tg1 _5 ch1tg1 _4 ch1tg1 _3 ch1tg1 _2 ch1tg1 _1 ch1tg1 _0 r/w cr11 0 1 0 1 1 ch2 ring ch2tg1 trp2 ch2tg1 trp1 ch2tg1 trp0 ch1 ri ng ch1tg1 trp2 ch1tg1 trp1 ch1tg1 trp0 r/w cr12 0 1 1 0 0 lv2r3 lv2r2 lv2r1 lv2r0 lv2x3 lv2x2 lv2x1 lv2x0 r/w cr13 0 1 1 0 1 f2_2 f1_2 f0_2 swc2 bsel2 e0_2 det2* alm2* r/w cr14 0 1 1 1 0 aout2 sel ch2tg tx ch2tg tout2 ch2tg2 lv3 ch2tg2 lv2 ch2tg2 lv1 ch2tg2 lv0 ch2tg2 _8 r/w cr15 0 1 1 1 1 ch2tg2 _7 ch2tg2 _6 ch2tg2 _5 ch2tg2 _4 ch2tg2 _3 ch2tg2 _2 ch2tg2 _1 ch2tg2 _0 r/w cr16 1 0 0 0 0 ch2tg1 lv6 ch2tg1 lv5 ch2tg1 lv4 ch2tg1 lv3 ch2tg1 lv2 ch2tg1 lv1 ch2tg1 lv0 ch2tg1 _8 r/w cr17 1 0 0 0 1 ch2tg1 _7 ch2tg1 _6 ch2tg1 _5 ch2tg1 _4 ch2tg1 _3 ch2tg1 _2 ch2tg1 _1 ch2tg1 _0 r/w cr18 1 0 0 1 0 ch2 loop1 ch2 loop0 ch1 loop1 ch1 loop0 test3 test2 test1 test0 r/w cr19 1 0 0 1 1 test11 test10 test9 test8 test7 test6 test5 test4 r/w *: read only bit note: in this datasheet, numbers in names for control regist er bits are often substituted by ?n? (in a small letter). in the case, the ?n? does not always refer to a channel number. ex) mode0, mode1 ? moden ch1tg2_7, ch1tg2_6 ? ch1tg2_n pmg2frq, pmg1frq ? pmgnfrq
fedl7033-04 ml7033 7/52 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd v ddd , v dda ?0.3 to +7.0 v analog input voltage v ain ? ?0.3 to v dd +0.3 v digital input voltage v din ? ?0.3 to v dd +0.3 v storage temperature t stg ? ?55 to +150 ? c recommended operating conditions parameter symbol conditio n min. typ. max. unit power supply voltage v dd voltage to be fixed; v ddd , v dda 4.75 5.0 5.25 v operating temperature t op ? ?40 ? +85 ? c high level input voltage v ih 2.2 ? v dd v low level input voltage v il all digital input pins 0 ? 0.8 v mck = 2.048 mhz mcksel (cr0-b5) bit = ?0? ?0.01% 2048 +0.01% khz mck frequency f mck mck = 4.096 mhz mcksel (cr0-b5) bit = ?1? ?0.01% 4096 +0.01% khz bclk frequency f bclk bclk 256 ? 4096 khz sync pulse frequency f sync xsync, rsync ?0.01% 8 +0.01% khz clock duty ratio d clk mck,bclk 40 50 60 % digital input rise time t ir ? ? 50 ns digital input fall time t if all digital input pins ? ? 50 ns mck to bclk phase difference t mb mck, bclk ? ? 50 ns t xs bclk to xsync 50 ? ? ns transmit sync pulse setting time t sx xsync to bclk 50 ? ? ns t rs bclk to rsync 50 ? ? ns receive sync pulse setting time t sr rsync to bclk 50 ? ? ns xsync, rsync short (cr0-b4) bit = ?0? 1 bclk ? 125 ? s ?1bclk ? s sync pulse width t ws xsync, rsync short (cr0-b4) bit = ?0? 210 ? 1bclk ns pcmout set-up time t ds pcmout 50 ? ? ns pcmout hold time t dh pcmout 50 ? ? ns r dl pull-up resistor, pcmout 0.5 ? ? k ? c dl1 pcmout ? ? 50 pf digital output load c dl2 other output pins ? ? 50 pf bypass capacitor for sgc c sg sgc to ag 0.1 ? ? ? f
fedl7033-04 ml7033 8/52 electrical characteristics dc and digital interf ace characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit i dd1 2ch operating mode, no signal ? 23.0 35.0 ma i dd2 1ch operating mode, no signal ? 16.0 22.0 ma power supply current i dd4 power-down mode pdn pin = logic ?0? ? 25.0 50.0 ? a high level input leakage current i ih all digital input pins v i = v dd ? 0.1 5.0 ? a low level input leakage current i il all digital input pins v i = 0 v ?5.0 ?0.1 ? ? a v ol1 pcmout , pull-up = 0.5 k ? 0 0.2 0.4 v digital output low voltage v ol2 other output pins, i ol = ?0.4 ma 0 0.2 0.4 v digital output high voltage v oh i oh = 0.4 ma 2.5 ? ? v digital output leakage current i o pcmout high impedance state ? ? 10 ? a input capacitance c in ? ? 5 ? pf analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit sg, sgc output voltage v sg sgc to ag 0.1 ? f ? 2.4 ? v sg, sgc rise time t sgc sgc to ag 0.1 ? f rise time to 90% of max. level ? ? 10 ms sg output load resistance r lsg sg 10 ? ? k ? transmit analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) parameter symbol conditio n min. typ. max. unit input resistance r inx ainnn, ainnp ? 10 ? m ? output load resistance r lgx 20 ? ? k ? output load capacitance c lgx ? ? 30 pf output amplitude v ogx gsxn (to sgc) *1 ? ? 2.226 vpp offset voltage v osgx gain = 1 ?50 ? 50 mv *1 ?3.0 dbm (600 ? ) = 0 dbm0
fedl7033-04 ml7033 9/52 receive analog interface characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) parameter symbol condit ion min. typ. max. unit r lao aoutnn, aoutnp (to sgc) 20 ? ? k ? output load resistance r lto toutn (to sgc) 10 ? ? k ? output load capacitance c lao aoutnn, aoutnp, toutn ? ? 50 pf output amplitude v oao aoutnn, aoutnp, toutn r lao = 20 k ? (to sgc) ? ? 3.4* vpp offset voltage v osao aoutnn, aoutnp, toutn r lao = 20 k ? (to sgc) ?100 ? 100 mv * 0.658 dbm (600 ? ) = 0 dbm0
fedl7033-04 ml7033 10/52 ac characteristics (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) condition parameter symbol freq. (hz) level (dbm0) min. typ. max. unit loss t1 60 25 45 ? loss t2 300 ?0.15 0.15 0.20 loss t3 1020 reference loss t4 3000 ?0.15 0.02 0.20 loss t5 3300 ?0.15 0.1 0.80 transmit frequency response loss t6 3400 0 gsxn to pcmout (attenuation) 0 0.6 0.80 db loss r1 100 ?0.15 0.04 0.2 loss r2 1020 reference loss r3 3000 ?0.15 0.07 0.2 loss r4 3300 ?0.15 0.2 0.8 receive frequency response loss r5 3400 0 pcmin to aoutn (attenuation) 0 0.6 0.8 db sdt1 3 36 43 ? sdt2 0 36 40 ? sdt3 ?30 36 38 ? sdt4 ?40 30 32 ? transmit signal to distortion ratio sdt5 1020 ?45 gsxn to pcmout *1 25 29 ? db sdr1 3 36 42 ? sdr2 0 36 39 ? sdr3 ?30 36 39 ? sdr4 ?40 30 33 ? receive signal to distortion ratio sdr5 1020 ?45 pcmin to aoutn *1 25 30 ? db gtt1 3 ?0.2 0.02 0.2 gtt2 ?10 reference gtt3 ?40 ?0.2 0.06 0.2 gtt4 ?50 ?0.6 0.4 0.6 transmit gain tracking gtt5 1020 ?55 gsxn to pcmout ?1.2 0.4 1.2 db gtr1 3 ?0.2 0 0.2 gtr2 ?10 reference gtr3 ?40 ?0.2 ?0.02 0.2 gtr4 ?50 ?0.6 ?0.1 0.6 receive gain tracking gtr5 1020 ?55 pcmin to aoutn ?1.2 ?0.2 1.2 db *1 c-message filter used
fedl7033-04 ml7033 11/52 ac characteristics (continued) (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) condition parameter symbol freq. (hz) level (dbm0) min. typ. max. unit nidle t ? ? analog input = sgc *1 ainn to pcmout gain = 1 ?? -law) ? 9 15 idle channel noise nidle r ? ? pcmin = ?ff?h ( ? -law) pcmin = ?d5?h (a-law) pcmin = all ?0? (linear) *1 pcmin to aoutn ? 4 10 dbm0 gsxn to pcmout v dd = 5 v, ta = 25 ? c 0.511 0.548 0.587 absolute level (initial difference) av t /av r pcmin to aoutn (single-ended) v dd = 5 v, ta = 25 ? c 0.806 0.835 0.864 vrms av tt ?0.3 ? 0.3 absolute level (deviation of temperature and power) av rt 1020 0 v dd = 4.75 to 5.25 v ta = ?40 to 85 ? c ?0.3 ? 0.3 db absolute delay t d 1020 0 a to a mode bclk = 2048 khz ? 0.58 0.6 ms t gd t1 500 ? 0.26 0.75 t gd t2 600 ? 0.16 0.35 t gd t3 1000 ? 0.02 0.125 t gd t4 2600 ? 0.05 0.125 transmit group delay t gd t5 2800 0 *2 ? 0.07 0.75 ms t gd r1 500 ? 0.00 0.75 t gd r2 600 ? 0.00 0.35 t gd r3 1000 ? 0.00 0.125 t gd r4 2600 ? 0.09 0.125 receive group delay t gd r5 2800 0 *2 ? 0.12 0.75 ms cr t trans to receive 75 83 ? cr r receive to trans 75 80 ? cross talk attenuation cr ch 1020 0 channel to channel 75 78 ? db discrimination dis 4.6 to 72k 0 0 to 4 khz 30 32 ? db out of band spurious obs 300 to 3.4k 0 4.6 to 1000 khz ? ?37.5 ?35 db sfd t ? ?50 ?40 signal frequency distortion sfd r 1020 0 0 to 4 khz ? ?48 ?40 dbm0 imd t ? ?50 ?40 intermodulation distortion imd r fa = 470 fb = 320 ?4 2 fa ? fb ? ?54 ?40 dbm0 psr t1 0 to 4k 40 44 ? psr t2 4 to 50k 50 55 ? psr r1 0 to 4k 40 45 ? power supply noise rejection ratio psr r2 4 to 50k 100 mvrms *3 50 56 ? db *1 c-message filter used *2 minimum value of the group delay distortion *3 under idle channel noise
fedl7033-04 ml7033 12/52 ac characteristics (continued) (v dd = 4.75 to 5.25 v, ta = ?40 to +85 ? c) parameter symbol condit ion min. typ. max. unit t sd ? ? 100 t xd1 ? ? 100 t xd2 pcmout pull-up resister = 0.5 k ? c l = 50 pf and 1 lsttl ? ? 100 ns t xd3 ? ? 100 digital output delay time t xd4 pcmosy , c l = 50 pf ? ? 100 ns pcmout operation delay time t ddo time to operation after power-down release ? 4 ? ms aoutn/toutn signal output delay time t dao time to baseband signal output after power-on ? 4 ? ms t 1 50 ? ? ns t 2 50 ? ? ns t 3 50 ? ? ns t 4 50 ? ? ns t 5 100 ? ? ns t 6 50 ? ? ns t 7 50 ? ? ns t 8 ? ? 50 ns t 9 20 ? ? ns t 10 20 ? ? ns t 11 ? ? 50 ns ? ? 3.5(*4) serial port i/o setting time t 12 c load = 50 pf 5.0(*4) ? ? ns exck clock frequency f exck exck 0.5 ? 10 mhz t 20 ? ? 200 ns t 21 ? 20 ? ? s t 22 ? ? 200 ns t 23 ? ? 200 ns slic interface delay time t 24 ? ? 225 ms *4 don?t raise the den in the range (3. 5ns to 5.0ns) delayed from falling edge of the 12 th exck.
fedl7033-04 ml7033 13/52 timing diagram transmit timing - 8-bit pcm mode with lin (cr0-b3) bit = ?0? long frame sync mode with short (cr0-b4) bit = ?0? mck bclk x sync pcmout p cmosy t xs d2 1 2345678 t sx t xd1 t sd d3 d4 d5 d6 d7 d8 msd t ws t xd2 t mb t xd3 t xd4 short frame sync mode with short (cr0-b4) bit = ?1? mck bclk xsync pcmout p cmosy t sx d2 1 2345678 t xs t xd1 d3 d4 d5 d6 d7 msd t ws t xd2 t mb t xd3 t xd4 d8 figure 1 transmit side timing diagram receive timing - 8-bit pcm mode with lin (cr0-b3) bit = ?0? long frame sync mode with short (cr0-b4) bit = ?0? t rs d2 1 2345678 t sr t ds t ws t dh d3 d4 d5 msd d6 d7 d8 t mb mck bclk rsync pcmin short frame sync mode with short (cr0-b4) bit = ?1? t sr d2 1 2345678 t rs t ds t ws t dh d3 d4 d5 msd d6 d7 t mb mck bclk rsync pcmin figure 2 receive side timing diagram note: the above timings are also valid in 14-bit linear pcm mode with the lin (cr0-b3) bit = ?1?, except that the number of dat a bits on the pcmin and pcmout signals changes from 8 to 14.
fedl7033-04 ml7033 14/52 pcm interface bit configuration 8-bit pcm mode with lin (cr0-b3) bit =?0? & long frame sync mode with short (cr0-b4) bit = ?0? bclk rsync pcmin pcmout p cmosy 1 9 17 25 1 msd d2 d3 d4 d5 d6 d7 d8 msd d2 d3 d4 d5 d6 d7 d8 msd d2 d3 ch1 pcm data ch2 pcm data 14-bit linear pcm mode with lin (cr0-b3) bit = ?1? & long frame sync mode with short (cr0-b4) bit = ?0? bclk rsync pcmin pcmout p cmosy 1 9 17 25 1 msd d2 d3 msd d10 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 ch1 linear data d13 d14 msd d10 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 ch2 linear data d13 d14 8-bit pcm mode with lin (cr0-b3) bit = ?0? & short frame sync mode with short (cr0-b4) bit = ?1? bclk rsync pcmin pcmout p cmosy 1 9 17 25 1 msd d2 d3 d4 d5 d6 d7 d8 msd d2 d3 d4 d5 d6 d7 d8 msd d2 d3 ch1 pcm data ch2 pcm data 14-bit linear pcm mode with lin (cr0-b3) bit = ?1? & short frame sync mode with short (cr0-b4) bit = ?1? bclk rsync pcmin pcmout p cmosy 1 9 17 25 1 msd d2 d3 msd d10 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 ch1 linear data d13 d14 msd d10 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 ch2 linear data d13 d14 figure 3 pcm interface bit configuration
fedl7033-04 ml7033 15/52 sgc, pcmout, and aout output timing pdn moden-bi t pcmou t sgc t ddo t dao aoutn sg level high impedance off on t sgc sg gnd high impedance figure 4 sgc, pcmout, and aout output timing
fedl7033-04 ml7033 16/52 mcu serial interface figure 5 mcu serial interface slic interface d en exck slic_i/f *5 e0_n 14 t 20 13 t 21 16 15 *5 slic_i/f = f2_n pin, f1_n pin, f0_n, swcn pin, bseln pin figure 6 slic interface 1 (to slic) t 24 a lm n , det n i n t (from almn ) i n t (from detn ) t 22 t 23 t 23 either a lmn pin or d et n pin,or den pin (cr6 and cr13) figure 7 slic interface 2 (from slic) * the int pin driven to a logic ?1? in either of the following cases ; (1) ( pdn pin = logic ?1?) any of the almn or detn pins (maximum 4 pins concerned) in a logic ?0? state go to logic ?1?. (2) ( pdn pin = logic ?0?) all of the almn or detn pins (maximum 4 pins concerned) in a logic ?0? state go to logic ?1?. (3) both slic 1 control (c r6) and slic 2 control (cr13) are read by the mcu. d en exck t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 11 t 10 dio (write) dio (read ) 1 2 3 4 5 6 13 14 15 w a 4 a 3 a 2 a 1 a 0 b1 b0 r a 4 a 3 a 2 a 1 a 0 b1 b0 t 12
fedl7033-04 ml7033 17/52 functional description pin functional description ain1n, ain1p, ain2n, ain2p, gsx1, gsx2 the ainnn and ainnp pins are the transmit path analog inputs for channel-n, where n equals channel 1 or channel 2. the ainnn pin is the inverting input, and the ainnp pin is the non-inverting input for the op-amp. the gsxn pin functions as the transmit path level adjustment for channel-n and is connected to the output of the op-amp. it is used to adjust the output level as shown in figure 8 below. when the ainnn or aininp pins are not in use, connect the ainnn pin to the gsxn pin and the ainnp pin to the sgc pin. during power-down mode, the gsxn output is in a high impedance state. in the case of the analog input 2.226 vpp at the gsxn pin, the digital output will be +3.00 dbm0. ch1 gain gain = r2/r1 ? 10 r1: variable r2 ? 20 k ? c1 ? 1/(2 ? 3.14 ? 30 ? r1) ch2 gain gain = r4/r3 ? 10 r3: variable r4 ? 20 k ? c2 ? 1/(2 ? 3.14 ? 30 ? r3) ch2 analog input gsx2 a in2n sgc r4 r3 c2 ch1 analog input gsx1 a in1n sgc r2 r1 c1 a in1p a in1p figure 8 example of analog input setting schematic aout1p, aout1n, aout2p, aout2n the aoutnn and aoutnp pins are the receive path analog outputs from channel-n, where n equals channel 1 or channel 2. these pins can drive a load of 20 k ? or more. when the aoutnsel register bit (cr7-b7/cr14-b7) is cleared (0), the aoutnp pin is a single-ended output from channel-n and the aoutnn pin is at high impedance. when the aoutnsel bit is set (1), the aoutnn and aoutnp pins are differentials outputs from the corresponding channel. the output signal from each of thes e pins has an amplitude of 3.4 vp p above and below the signal ground voltage (sg). hence, when the maximum pcm code (+3.00 dbm0) is input to the pcmin pin, the maximum amplitude between the aoutnn pin an d the aoutnp pin will be 6.8 vpp. while the device is in power-down mode, or the corresponding channel (1 or 2) is in power saving mode, the related outputs are high impedance. refer to table 5 for more information.
fedl7033-04 ml7033 18/52 tout1, tout2 toutn is the tone analog output for the corresponding channel. the output signal has an amplitude of 2.5 vpp above and below the signal ground voltage (sg). while the device is in power-down mode, or the corresponding channel is in power-save mode, the related outputs are high impedance. v dda , v ddd +5 v power supply for analog and digital circuits. the v dda pin is the power pin for the analog circuits. the v ddd pin is the power pin for the digital circuits. if these signals are connected together externally, the v dda pin must be connected to the v ddd pin in the shortest distance on the printed circuit board. internal to the ml7033, the v dda plane is separate from the v ddd plane. to minimize power supply noise, a 0.1 ? f bypass capacitor (with excellent hi gh frequency characteristics) and a 10 ? f electrolytic capacitor should be connected between the v dda pin and the ag pin. in addition, the same capacitive network should also be connected between the v ddd pin and the dg pin. if the ag and dg pins are connected together externally, only one capacitive network is required. ag, dg the ag pin is a ground for the an alog circuits. the dg pin is a ground for the digital circuits. the analog ground and the digital ground are separated internally within the device. the ag pin and dg pins must be connected in the shortest distance on the printed circuit board, and then to system ground with a low impedance. sgc the sgc pin used is to internally generate the signal ground voltage level by connecting a bypass capacitor. the output impedance is approximately 50 k ? . connect a 0.1 ? f bypass capacitor with excellent high frequency characteristics between the sgc pin and the ag pin. during power-down mode, the sgc output is at the voltage level of the ag pin. sg the sg pin is the signal ground level output for the system circuits. the output voltage is 2.4 v, the as same as the sgc pin in a normal operating state. during power-down mode, this output is high impedance. mck master clock input. input either 2.048 or 4.096 mhz clock. after turning on the power, the appropriate value must be written into the mcksel bit (cr0-b5) depending upon the desired master clock frequency. if the supplied master clock frequency and the value of the mcksel bit (cr0-b5) do not match, the power-down control circuit and the mcu interface circuit will continue to operate properly. access to the control registers can also occur. however, other circuits may not operate properly. as for the power-on sequence, please refer to ?power-on sequence? in the later page.
fedl7033-04 ml7033 19/52 bclk shift clock signal input for the pcmin and the pcmout signals. the clock frequency, equal to the data rate, is 256 khz to 4096 khz. this signal must be generated from the same clock source as the master clock and synchronized in phase with the mast er clock. please refer to figures 1 and 2 for more information about the phase difference between mck and bclk. rsync receive synchronizing clock input. the pcmin signals ar e received in synchronization with this clock. the 8 khz input clock is generated from the identical clock source as mck and must be synchronized in phase with the master clock. xsync transmit synchronizing clock input. the pcmout signals are transmitted in synchronization with this clock. the 8 khz input clock is generated from the identical clock source as mck and must be synchronized in phase with the master clock. pcmin serial pcm data input. the serial pcm data input on th e pcmin pin is converted to analog signals and output from the aoutnp pin (or from the aoutnn pin and the aoutnp pin) in synchronization with the rsync clock and the bclk clock. when in long frame sync mode (cr0-b4 = ?0?), the first bit of the serial pcm data (msd of channel 1) is identified at the rising edge of the rsync clock. when in short frame sync mode (cr0-b4 = ?1?), the first bit of the serial pcm data (msd of channel 1) is identified at the falling edge of the rsync clock. pcmout serial pcm data output. channel 1 data is output in sequential order, from most significant data (msd) to least significant data (lsd). data is synchronized with the rising edge of bclk. when in long frame sync mode (cr0-b4 = ?0?), the first bit of pcm data may be output at the rising edge of the xsync signal, depending on the timing between bclk and xsync. when in short frame sync mode (cr0-b4 = ?1?), the first bit of pcm data may be output at the falling edge of the xsync signal, depending on the timing between bclk and xsync. this pin is in a high impedance state during power-down. a pull-up resistor must be connected to this pin since it is an open drain output. pcmosy pcmosy is asserted to a logic 0 when pcm data is valid on the pcmout pin. this includes both normal mode and power-save mode. when pcm data is not being output from the pcmout pin (including during power-down mode), this pin goes a logic ?1?. this signal is used to control the tri-s tate enable of a backplane line-driver.
fedl7033-04 ml7033 20/52 table 1 pcm codes in 8-bit pcm mode with the lin (cr0-b3) bit = ?0? pcmin/pcmout alaw (cr0-b2) bit = ?0? ( ? -law ) alaw (cr0-b2) bit = ?1? (a-law ) input/output level msd d2 d3 d4 d5 d6 d7 d8 msd d2 d3 d4 d5 d6 d7 d8 +full scale 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 +0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 ?0 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 ?full scale 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 table 2 pcm codes in 14-bit linear pcm mode with the lin (cr0-b3) bit = ?1? pcmin/pcmout input/output level msd d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 +full scale 0 1 1 1 1 1 1 1 1 1 1 1 1 1 +1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ?full scale 1 0 0 0 0 0 0 0 0 0 0 0 0 0 pdn power-down control signal. when pdn is a asserted (logic ?0?), both the channel 1 and channel 2 circuits enter the power-down state. howeve r, even in power-down mode, the state of the control registers is maintained. reads and writes to the registers are also possible, and the state of the int pin also changes in accordance with inputs from the slic devices. this pin is deasserted (logic ?1?) by external logic during normal operation. this power-down function is available even in power saving mode by the moden (cr0-b1/cr0-b0) bit. reset an input to reset control re gisters. by asserting the reset pin (applying a logic ?0?), all control registers are initialized. during a normal operation mode, set this pin logic ?1?. table 3 state of pcmout in 8-bit pcm mode with lin (cr0-b3) bit = ? 0 ? pdn pin mode1 bit mode0 bit alaw bit ch2 pcm data ch1 pcm data 0 0/1 0/1 0/1 hi-z *1 hi-z *1 0 11111111 11111111 1 0 0 1 11010101 11010101 0 1 1 1 1 1 1 1 1 operate 1 0 1 1 1 1 0 1 0 1 0 1 operate 0 operate 1 1 1 1 1 1 1 1 1 1 0 1 operate 1 1 0 1 0 1 0 1 0 operate operate 1 1 1 1 operate operate
fedl7033-04 ml7033 21/52 table 4 state of pcmout in 14-bit linear pcm mode with lin (cr0-b3) bit = ?1? pdn pin mode1 bit mode0 bit alaw bit ch2 pcm data ch1 pcm data 0 0/1 0/1 hi-z *1 hi-z *1 1 0 0 all ?0? all ?0? 1 0 1 all ?0? operate 1 1 0 operate all ?0? 1 1 1 0/1 operate operate table 5 state of analog output pins pdn pin mode1 bit mode0 bit gsx1 pin gsx2 pin aout1 pin aout2 pin sg pin sgc pin mcu interface 0 0/1 0/1 hi-z hi-z hi-z hi-z hi-z ag level *2 operate 1 0 0 hi-z hi-z hi-z hi-z hi-z ag level *2 operate 1 0 1 operate hi-z operate hi-z operat e operate operate 1 1 0 hi-z operate hi-z oper ate operate oper ate operate 1 1 1 operate oper ate operate operate oper ate operate operate *1 the data will be ?h? by an external pull-up resistor. *2 output impedance = about 50 k ? f2_1, f1_1, f0_1, f2_2, f1_2, f0_2 the f2_n, f1_n and f0_n pins are data outputs used when the slic connected to the corresponding channel is an intersil rslic tm series device. the output levels from the f2_n, the f1_n and f0_n pins are determined by the f2_n, f1_n, and f0_n register bits (cr6-b7 to b5 an d cr13-b7 to b5). by inputting these outputs directly into the corresponding input pin of the slic device, the slic operating mode selection is possible. even in the power- down state with the pdn pin is asserted, these pins remain functional. e0_1, e0_2 the e0_n pins are the detector mode selection data output s. these pins are used when the slic connected to the corresponding channel is an intersil rslic tm series device. though the output level from the e0_n pin is determined by the e0_n bit (cr6-b2/cr13-b2), the output level changes in 20 ? s (= hold timer) in the power-on mode with the pdn pin = logic ?1? and in 200 ns in the power-down mode with the pdn pin = logic ?0? after the change of e0_n bit (cr6-b2 /cr13-b2). refer to figure 6 for information. what event is actually detected by the slic is determined by the combination of the f2_n, f1_n, f0_n and e0_n pins. refer to table 6 for more information. by connectin g the output directly into the corresponding input pin of the slic device, detector mode selection in the slic is possible. even in the power-down state with the pdn pin = logic ?0?, this pin remains functional. howe ver, the hold timer is ignored in this state.
fedl7033-04 ml7033 22/52 table 6 slic device operation mode and detector mode operating mode f2_n f1_n f0_n e0_n = 1 e0_n = 0 description low power standby 0 0 0 shd gkd standby mode forward active 0 0 1 shd gkd forward battery loop feed unbalanced ringing 0 1 0 rtd rtd unbalanced ringing mode reverse active 0 1 1 shd gkd reverse battery loop feed ringing 1 0 0 rtd rtd balanced ringing mode forward loop back 1 0 1 shd gkd test mode tip open 1 1 0 shd gkd for pbx type application power denial 1 1 1 n/a n/a device shutdown shd: switch hook detection rtd: ring trip detection gkd:ground key detection bsel1, bsel2 the bseln pin is the battery mode selection data output. this pin is used when the slic connected to the corresponding channel is an intersil rslic tm series slic device. a logic ?0? on this pin selects the low battery mode, and the logic ?1? selects the high battery mode within the slic device. the output levels from the bseln pins are determined by the bseln register bits (cr6-b3/cr13-b3). by connecting these outputs directly to the corresponding slic device input pins, battery mode selection of the slic is possible. this pin remains functional even in power-down mode. swc1 , swc2 the swcn pin is the uncommitted switch control data output. this pin is used when the slic connected to the corresponding channel is an intersil rslic tm series slic device. by connecting this pin directly to the corresponding input pin of the slic device, the uncommitted switch control can be made. the uncommitted switch is located between the sw+ pin and the sw- pin. a logic ?0? on this pin enables the slic internal switch on, and a logic ?1? disables the switch. the output levels from the swc1 and swc2 pins are determined by the swcn register bits (cr6-b4/cr13-b4). this pin remains functional even in power-down mode with the pdn pin is a logic ?0?. det1 , det2 the detn pins are the slic?s detection signal (switch hook, ring trip or ground key detection) inputs. these pins are used when the slic connected to th e corresponding channel is an intersil rslic tm series device. a logic ?0? on this pin clears the corresponding detn register bit (cr6-b1/cr13-b1). a logic ?1? on this pin input sets the register bit. the intersil rslic tm series slic device is equipped with a function to switch the output on its det pin from a logic ?1? state to a logic ?0? state when it detects an assign ed event of either off-hook, ring trip or ground key. therefore, by connecting these pins to the corresponding pins on the slic device and reading the detn register bit (cr6-b1/cr13-b1), the occurrence of an assigned event can be detected.
fedl7033-04 ml7033 23/52 the event detected by the slic is determined by the f2_n, f1_n, and f0_n register bits (cr6-b7 to b5/cr13-b7 to b5), and the e0_n register bits (cr6-b2 /cr13-b2). to avoid the unintended detection of these conditions due to glitches on the detn signal of the slic, the ml7033 is equipped with a debounce timer to hold the det register bit (cr6-b1/cr13-b1) and the output of the int pin for a set period, even when an input to the detn pin changes from a logic ?1? to a logic ?0?. for more information on the debounce timer, refer to the detntim3 through detntim0 register bit descriptions (cr4-b7 to b0). this pin remains functional in power-down mode ( pdn pin low). however, while in the power-down state, the debounce timer is disabled. when this pin is not used, it should be tied to v ddd . alm1 , alm2 the almn pins are the thermal shut down alarm signals. thes e pins are used when the slic connected to the corresponding channel is an intersil rslic tm series device. a logic ?0? on the almn input pin clears the corresponding alm register bit (cr6-b0/cr13-b0). a logic ?1? on this pin sets the bit. the intersil rslic tm series device is equipped with a function th at allows it to automatically enter power-down mode and toggle its almn pin from a logic ?1? to a logic ?0? stat e when the slic die temperature exceeds a safe operating temperature. hence, by connecting the corresponding pin of the slic device to the alm1 and alm2 pins and reading the alm register bit (cr6-b0/cr13-b0), it is possible to know whether the concerned slic device is operating normally, or is in a thermal shutdown state. this pin remains functional in power-down mode. however, while in the power-down state, the debounce timer is disabled. when this pin is not used, it should be tied to v ddd . int the ml7033 asserts the int interrupt pin when either the detn pin or the almn pin are asserted by the slic device when the device is an intersil rslic tm series slic device. the intersil rslic tm series device is equipped with detector and thermal shut down alarm functions to notify a change of slic state by driving a logic 0 onto the output pins connected to detn and almn . refer to the detn and almn pin descriptions above. by monitoring the state of the int pin and reading the detn (cr6-b0/cr13-b0) and almn (cr6-b0/cr13-b0) register bits, it is possible to know that a change of a state occurred within the slic device. the int pin transitions from a logic ?1? to a logic ?0? in the following cases; (1) ( pdn pin = logic ?0?) any of the almn or detn pins in the logic ?1? state transition to the logic ?0? state. (2) ( pdn pin = logic ?1?) any of the almn or detn pins transition from the logi c ?1? state to the logic ?0? state when all the four pins ( alm1 , alm2 , det1 , and det2 ) have been in the logic ?1? state. note that the debounce timer with the detn pin is not valid while in power-down mode ( pdn pin = logic ?0?).
fedl7033-04 ml7033 24/52 the int pin is released to the logic ?1? state in either of the following cases; (1) ( pdn pin = logic ?1?) any one of the almn or detn pins in the logic ?0? state transition to the logic ?1? state. (2) ( pdn pin = logic ?0?) all of the almn or detn pins in the logic ?0? state transition to the logic ?1? state. (3) both slic 1 control (cr6 register) and slic 2 control (cr13 register) are read by the mcu. note that the debounce tim er, which works when the detn pin changes from a logic ?1 ? state to a to logic ?0? state, does not work when the pin ch anges from logic ?0? to logic ?1?. den , exck, dio serial control ports for the mcu interface. these pins are used by an external mcu to access the internal control registers of the ml7033. the den pin is the data enable input. the exck pin is the data shift clock input. the dio pin is the address and data input/output. figure 9 shows the mcu interface input/output timing diagram. note that exck must be a continuous cl ock of at least 15 pulses or more. r a4 a3a2a1a0 b7b6b5b4 b3b2b1b0 exck den dio (i) w a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 exck den dio (o) write timing read timing input output figure 9 mcu interface timing diagram cidata1, cidata2 the cidata1 and cdata2 data inputs are used for calle r id generation. while in a caller id tone generation mode with the cidchnon register bit set, (cr1-b1/cr1-b0), signals on the cidatan pins are modulated in either the itu-t v.23 or bell 202 schemes. the scheme is determined by the cidfmt register bit (cr1-b2), and output from the analog output pin(s). the analog output pins for modulated caller id data can be selected by the chntg2tx (cr7-b6/cr14-b6), the chntgtoutn (cr7-b5/cr14-b5), and the aoutnsel (cr7-b7/cr14-b7) register bits. the output level for the modulated caller id data can be tuned by the chntg1lvn (cr9-b7 to b1/cr16-b7 to b1) register bits. test the test input is used for testing purposes only during the manufacturing process and has no function once the testing process is completed. this pin is not used during normal operation of the device and should be kept at a logic ?0? state.
fedl7033-04 ml7033 25/52 power-on sequence while in the power-on state, the following chart is recommended. figure 10 power-on sequence flow chart as the ml7033 is equipped with a power-on reset function, initialization of the control registers automatically occurs as the power is turned on, even with the reset pin = logic ?1?. however, if any of input pins are not in a high impedance state, the power-on reset may not function properly. control register setting (ch1/ch2) normal operation pdn pin = ?1? even during power-down mode with the pdn pin = logic ?0?, the slic interface registers (cr6, cr13) and the int pin are working. data set in other registers becomes valid after the pdn pin is driven to a logic ?1? state. power off power supply on pdn pin = logic ?0?, reset pin= ?0? rese t pin = ?0? to ?1? (or power-on reset function) keep the input to the r ese t pin in the logic ?0? state for 100ns or longer before changing to a logic ?1?. < note >
fedl7033-04 ml7033 26/52 control registers functional description cr0 (basic operating mode) b7 b6 b5 b4 b3 b2 b1 b0 cr0 filter1sel filter2sel mc ksel short lin alaw mode1 mode0 default 0 0 0 0 0 0 0 0 b7 ? transmit and receive filter select for ch1 0 : itu-t g.714 filter 1 : wideband filter for v.90 data modem application b6 ? transmit and receive filter select for ch2 0 : itu-t g.714 filter 1 : wideband filter for v.90 data modem application b5 ? mck frequency select 0 : 2.048 mhz 1 : 4.096 mhz b4 ? frame synchronizing scheme select 0 : long frame sync 1 : short frame sync refer to figure 3. b3 ? pcm companding law select 0 : 8-bit pcm mode 1 : 14-bit linear pcm (2?s complement) mode ?1? is selected, a setting with the alaw (cr0-b2) bit is ignored. b2 ? pcm companding law select 0 : ? -law 1 : a-law when the lin (cr0-b3) is ?1?, a setting with this bit is ignored. b1, b0 ? power saving control 0 : power saving mode 1 : normal operation the mode1 (cr0-b1) bit is for channel 2, and the mode0 (cr0-b0) bit is for channel 1. in power saving mode, power for the corresponding channel is turned off except for the last output stage of the pcmout pin. the power saving mode differs from the power-down mode controlled by the pdn pin in the following aspects; - possible to control a state for an individual channel independently - the last stage of the pcmout pin is operational, and outputs ?positive zero? pcm code in the 8-bit pcm mode or ?zero? pcm code in the 14-bit linear pcm mode during the assigned time slot. - debounce timer and hold timer are valid. as in power-down mode, the power saving mode does not initialize control registers and read and write of control registers are possible in the power saving mode. the power-down mode setting by the pdn pin takes precedence over the power saving mode. table 7 mode settings for ch1 and ch2 power of channel mode1 bit mode0 bit pdn pin reset pin ch2 ch1 register 0 *1 0 *1 0 0 off off initialized to default 0 *1 0 *1 1 0 off *2 off *2 initialized to default 0/1 0/1 0 1 off off read/write possible 0 0 1 1 off *2 off *2 read/write possible 0 1 1 1 off *2 on read/write possible 1 0 1 1 on off *2 read/write possible 1 1 1 1 on on read/write possible *1 forced to be default by the reset pin = logic ?0?. *2 the last output stage is powered.
fedl7033-04 ml7033 27/52 cr1 (tone generator and call id tone control) b7 b6 b5 b4 b3 b2 b1 b0 cr1 ch2tg on ch1tg on cidfmt cid ch2on cid ch1on default 0 0 0 0 0 0 0 0 b7 ? state control for a tone generator on chl 0 : disabled 1 : enabled b6 ? state control for a tone generator on ch2 0 : disabled 1 : enabled b5, b4, b3 ? reserved (the defa ult alternation is prohibited.) when a write action is executed for cr1, set these bits to ?0?. b2 ? caller id generator modulation scheme select 0 : itu-t v.23 scheme (1: 1300 hz, 0: 2100 hz) 1 : bell 202 format (1: 1200 hz, 0: 2200 hz) b1 ? state control for caller id generator on ch2 0 : off 1 : on regardless of how the ch2tgon bit (cr1-b7) is set, signals input into the cidata2 pin are modulated and output as caller id tones. wh en this bit is set, the level setting by the ch2tg1lvn (cr16-b7 to b1) bits is valid, but the ch2tg1_n (cr16-b0/cr17-b7 to b0) bits, ch2ring (cr11-b7) bit, and ch2tg1trpn (cr11-b6 to b4) bits are invalid. b0 ? state control for caller id generator on ch1 0 : off 1 : on regardless of how the ch1tgon bit (cr1-b6) is set, signals input into the cidata1 pin are modulated and output as caller id tones. when this bit is set, the level set by the ch1tg1lvn (cr9-b7 to b1) bits is valid, but the ch1tg1_n (cr9-b0/cr11-b7 to b0) bits, the ch1ring (cr11-b3) bit, and the ch1tg1trpn (cr11-b2 to b0) bits are invalid.
fedl7033-04 ml7033 28/52 cr2 (pulse metering tone generator control) b7 b6 b5 b4 b3 b2 b1 b0 cr2 pmg2 frq pmg2 lv1 pmg2 lv0 pmg2 tout2 pmg1 frq pmg1 lv1 pmg1 lv0 pmg1 tout1 default 0 0 0 0 0 0 0 0 b7 ? pulse metering tone frequency select for ch2 0 : 12 khz 1 : 16 khz b6, b5 ? pulse metering tone level setting for ch2 (b6, b5) (0, 0) = off (0, 1) = 0.5 vpp (1, 0) = 1.0 vpp (1, 1) = 1.5 vpp the level of the pulse metering tone, as shown in figure 11, reaches the assigned level in 10 ms and gradually fades out over 10 ms. the ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0) into these register bits. once the register bits are set, the tone begins to fade out and completely fades out after 10 ms. in addition, subsequent writes to these bits are prohibited for 10 ms. figure 11 pulse metering tone waveform b4 ? pulse metering tone output pin select for ch2 0 : aout2 pin (added to voice signals) 1 : tout2 pin b3 ? pulse metering tone frequency select for ch2 0 : 12 khz 1 : 16 khz b2, b1 ? pulse metering tone level setting for ch1 (b2, b1) (0,0) = off (0, 1) = 0.5 vpp (1, 0) = 1.0 vpp (1, 1) = 1.5 vpp the level of the pulse metering tone, as shown in figure 11, reaches the assigned level in 10 ms and gradually fades over 10 ms. the ramp-up and ramp-down times also apply when a tone is cancelled by writing (0,0) into these register bits. in this case the tone fades out after 10 ms. in addition, subsequent writes to these bits are prohibited for 10 ms. b0 ? pulse metering tone frequency select for ch1 0 : 12 khz 1 : 16 khz ramp up time=10ms ramp down time=10ms
fedl7033-04 ml7033 29/52 cr3 (time slot assignment control) b7 b6 b5 b4 b3 b2 b1 b0 cr3 tsae tsac tsa5 tsa4 tsa3 tsa2 tsa1 tsa0 default 0 0 0 0 0 0 0 0 * cr3 is a write only register. b7 ? time slot assignment customization enable 0 : default time slot assignment 1 : customized time slot assignment the default time slot assignment is ch1 for slot 0 and ch2 for slot 2. b6 ? time slot assignment channel select 0 : ch1 1 : ch2 this bit is used to specify the channel for which the accompanied tsan (cr3-b5 to b0) bits are going to assign a time slot. hence, when a customized time slot assignment is enabled, cr3 should be written twice; once for ch1 and another for ch2. b5 to b0 ? assigned time slot select each time slot consists of 8 bclk cycles. th e number of time slots available for time slot assignment depends upon the applied bclk frequency, and can be calculated in the following equations; number of time slots available for time slot assignment = (bclk frequency)/(sync frequency)/8 = (bclk frequency)/64k for instance, when the bclk frequency is 4096 khz, time slots that can be assigned are from 0 (000000) to 63 (111111). the specification of a time slot beyond 63 is prohibited. note that in 14-bit linear pcm (2?s complement) mode, specified when the lin bit (cr0-b3) is set, only even numbered time slots (0, 2, 4, ? 62) can be assigned. in any mode, the assigned time slot for a channel is common both for transmit and receive, and different time slots cannot be assigned for transmit and receive. when the tsae bit (cr3-b7) is cleared, the time slot assignment specified by these bits is ignored, and the default time slots are assigned (ch1 for time slot 0 and ch2 for time slot 2). figure 12 shows an example of how ch1 is assigned for time slot 0 (000000) and ch2 is assigned for time slot 3 (000011) in 8-bit pcm mode. msd d2 d3 d4 d5 d6 d7 d8 bclk x sync pcmout/ pcmin p cmosy 1 9 17 25 33 ch1 pcm data msd d2 d3 d4 d5 d6 d7 d8 ch2 pcm data slot 0 slot 1 slot 2 slot 3 figure 12 example of time slot assi gnment: ch1 = slot 0, ch2 = slot 3
fedl7033-04 ml7033 30/52 cr4 (debounced timer setting) b7 b6 b5 b4 b3 b2 b1 b0 cr4 det2 tim3 det2 tim2 det2 tim1 det2 tim0 det1 tim3 det1 tim2 det1 tim1 det1 tim0 default 0 0 0 0 0 0 0 0 b7 to b4 ? debounce timer setting for ch2 b3 to b0 ? debounce timer setting for ch1 to avoid the unintended detection of glitches on the detn signal, the ml7033 is equipped with a debounce timer to hold the detn (cr6-b1/cr13-b1) bit and the int output state for a set period, even when the state of the detn pin changes from logic ?1? to logic ?0?. bits b7 to b4 determine the debounce timer setting for ch2. bits b3 to b0 determine the debounce timer setting ch1. the debounce timer is operational only in the power-on state when the pdn pin = logic ?1?, and remains operational in the power-saving mode with the moden (cr0-b1, b0) bits = ?0? as long as the device is in the power-on state. the debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each individual channel. the values written into b7 to b4 (channel 2) or b3 to b0 (channel 1) determine the holding time for each channel. the timer value is calculated by the equation of [decimal(b7,b6,b5,b4) * 15] or [decimal(b3,b2,b1,b0) * 15]. refer to table 8. table 8 debounce timer setting b7/b3 b6/b2 b5/b1 b4/b0 timer (ms) 0 0 0 0 0 0 0 0 1 15 0 0 1 0 30 0 0 1 1 45 0 1 0 0 60 : : : : : 0 1 1 1 105 1 0 0 0 120 1 0 0 1 135 : : : : : 1 1 1 1 225
fedl7033-04 ml7033 31/52 cr5 (ch1 transmit/receive level control) b7 b6 b5 b4 b3 b2 b1 b0 cr5 lv1r3 lv1r2 lv1r1 lv1r0 lv1x3 lv1x2 lv1x1 lv1x0 default 0 0 0 0 0 0 0 0 b7 to b4 ? level setting for ch1 on its receive side the lv1r3 to lv1r0 bits determine the level for the ch1 receive side as shown in table 9. b3 to b0 ? level setting for ch1 on its transmit side the lv1x3 to lv1x0 bits determine the level for the ch1 transmit side as shown in table 9. table 9 receive and transmit level setting lv1r3/lv1x3 lv1r2/ lv1x2 lv1r1/ lv1x1 lv1r0/lv1x0 level (dbm0) 0 0 0 0 0.0 0 0 0 1 ?1.0 0 0 1 0 ?2.0 0 0 1 1 ?3.0 0 1 0 0 ?4.0 0 1 0 1 ?5.0 0 1 1 0 ?6.0 0 1 1 1 ?7.0 1 0 0 0 ?8.0 1 0 0 1 ?9.0 1 0 1 0 ?10.0 1 0 1 1 ?11.0 1 1 0 0 ?12.0 1 1 0 1 ?13.0 1 1 1 0 ?14.0 1 1 1 1 off
fedl7033-04 ml7033 32/52 cr6 (slic 1 control) b7 b6 b5 b4 b3 b2 b1 b0 cr6 f2_1 f1_1 f0_1 swc1 bsel1 e0_1 det1 alm1 default 0 0 0 0 0 0 ? ? * cr6-b1 and b0 are read-only bits. though either of ?0? or ?1? will do for these registers when a byte-wide write action is made, the written values are ignored. * the int pin which stays at logic ?0? will be released to logic ?1? when both of this control register (cr6) and slic 2 control register (cr13) are read. b7 to b5 ? operation mode setting for slic1 the f2_1 to f0_1 bits determine the output level for the fn_1 pins. for more details, refer to table 6. when each bit is cleared (?0?), the corresponding fn_1 pin outputs a logic ?0?. when each bit is set (?1?), the corresponding fn_1 pin outputs a logic ?1?. b4 ? uncommitted switch control for slic1 0 : switch on 1 : switch off this bit determines the output level for the swc1 pin. when this bit is cleared, the swc1 pin outputs a logic ?0?. when this bit is set, the pin outputs a logic ?1?. when the slic connected to ch1 is the intersil rslic tm series, the slic?s internal uncommitted switch, located between the sw+ pin and the sw- pin, can be controlled by inputting the output from the swc1 pin directly into the corresponding input pin of the slic device. b3 ? battery mode select for slic1 0 : low battery mode 1 : high battery mode this bit determines the output level for the bsel1 pin. when this bit is cleared, the bsel1 pin outputs a logic ?0?. when this bit is set, the pin outputs a logic ?1?. when the slic connected to ch1 is from the intersil rslic tm series, the slic?s battery mode selection is possible by inputting the output from the bsel1 pin directly into the corresponding input pin of the slic device. b2 ? detector mode selection for slic1 this bit determines the output level for the e0_1 pin. when this bit is cleared, the e0_1 pin outputs a logic ?0?. when this bit is set, the pin outputs a logic ?1?. when a slic connected to ch1 is intersil rslic tm series, the slic?s detector mode selection is possible by connecting the e0_1 pin directly to the corresponding input pin of the slic device. the event detected by the sl ic is determined by the combination of the f2_1, the f1_1, the f0_1 and the e0_1 pins as shown in table 6. the output level of the e0_1 pin changes 20 ? s later (hold timer) in the power-on mode with the pdn pin = logic ?1?, and 200ns later in the power-down mode with the pdn pin = logic ?0? than a change of this bit value. refer to figure 6.
fedl7033-04 ml7033 33/52 b1 ? event detection indicator for slic1 (read-only bit) 0 : detected 1 : not detected by reading the state of this bit, the input level to the det1 pin can be known. if this bit is cleared it indicates that the det1 pin is in the logic ?0? state. if this bit is set it indicates that the det1 pin is in the logic ?1? state. when the slic connected to channe l 1 is from the intersil rslic tm series, the det1 pin can be connected directly to the corresponding output pin of the slic device. this allows an assigned event such as off-hook, ring trip, or ground key to be detected. the event detected by the slic detects is determined by the f2_1, f1_1, f0_1 (cr6-b7 to b5), and e0_1 (cr6-b2) bits. when the debounce timer is enabled by setting the det1tim3 through det1tim0 bits (cr4-b3 to b0), the det1 (cr6-b1) bit is held unchanged for a set period, even when the det1 input pin changes from logic ?1? to logic ?0?. b0 ? thermal shutdown alarm indicator for slic1 (read-only bit) 0 : detect 1 : not detect by reading this bit, the input level to the alm1 pin can be known. when this bit is cleared, the alm1 pin is a logic ?0?. when this bit is set, the pin is a logic ?1?. when the slic connected to chan nel 1 is from the intersil rslic tm series, the alm1 pin can be connected directly to the corresponding output pin of the slic device. this allows the user to know whether the slic1 is in the normal operating state, or in the thermal shutdown state.
fedl7033-04 ml7033 34/52 cr7 (ch1 tone generator 2 control 1) b7 b6 b5 b4 b3 b2 b1 b0 cr7 aout1 sel ch1tg 2 tx ch1tg 2 tout1 ch1tg2 lv3 ch1tg2 lv2 ch1tg2 lv1 ch1tg2 lv0 ch1tg2 _8 default 0 0 0 0 0 0 0 0 cr8 (ch1 tone generator 2 control 2) b7 b6 b5 b4 b3 b2 b1 b0 cr8 ch1tg2 _7 ch1tg2 _6 ch1tg2 _5 ch1tg2 _4 ch1tg2 _3 ch1tg2 _2 ch1tg2 _1 ch1tg2 _0 cr7-b7 ? aout1p, aout1n output select 0 : single-ended output with the aout1p pin with the aout1n pin at high impedance 1 : differential output with the aout1p and the aout1n pins b6 ? ch1 tone generator output select 0 : to rx side 1 : to tx side b5 ? ch1 tone generator rx side output pin select 0 : aout1 pin 1 : tout1 pin b4 to b1 ? ch1 tone generator 2 (tg2) output level setting this 4-bit field defines the output level for tg2 on ch1 as shown in table 10. table 10 tg2 level setting b4 (tg2lv3) b3 (tg2lv2) b2 (tg2lv1) b1 (tg2lv0) level (dbm0) 0 0 0 0 off 0 0 0 1 ?12.0 0 0 1 0 ?11.0 0 0 1 1 ?10.0 0 1 0 0 ?9.0 0 1 0 1 ?8.0 0 1 1 0 ?7.0 0 1 1 1 ?6.0 1 0 0 0 ?5.0 1 0 0 1 ?4.0 1 0 1 0 ?3.0 1 0 1 1 ?2.0 1 1 0 0 ?1.0 1 1 0 1 0.0 1 1 1 0 +1.0 1 1 1 1 +2.0
fedl7033-04 ml7033 35/52 cr7-b0, cr8-b7 to b0 ? ch1 tone generator 2 (tg2) frequency select these bits define the output frequency from tg2 on ch1. the frequency is between 300 and 3400hz at 10hz intervals. the values writte n to these bits determine the frequency as shown in the following equation. refer to table 11. binary data for cr7-b0, cr8-b7 to b0 = (output frequency [hz])/10 below is an example of how these bits are programmed when the intended frequency is 1500hz; ex) (output frequency [hz])/10 = 1500/10 = 150d = 10010110b bits to set in cr7-b0, cr8-b7 to b0 = (0,1,0,0,1,0,1,1,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 300 and 3400 hz. table 11 tone generator frequency setting cr7 cr8 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 300 30 01eh 0 0 0 0 1 1 1 1 0 310 31 01fh 0 0 0 0 1 1 1 1 1 320 32 020h 0 0 0 1 0 0 0 0 0 : : : : : : : : : : : : 400 40 028h 0 0 0 1 0 1 0 0 0 410 41 029h 0 0 0 1 0 1 0 0 1 : : : : : : : : : : : : 1000 100 064h 0 0 1 1 0 0 1 0 0 1010 101 065h 0 0 1 1 0 0 1 0 1 : : : : : : : : : : : : 2000 200 0c8h 0 1 1 0 0 1 0 0 0 : : : : : : : : : : : : 3000 300 12ch 1 0 0 1 0 1 1 0 0 : : : : : : : : : : : : 3390 339 153h 1 0 1 0 1 0 0 1 1 3400 340 154h 1 0 1 0 1 0 1 0 0
fedl7033-04 ml7033 36/52 cr9 (ch1 tone generator 1 control1) b7 b6 b5 b4 b3 b2 b1 b0 cr9 ch1tg1 lv6 ch1tg1 lv5 ch1tg1 lv4 ch1tg1 lv3 ch1tg1 lv2 ch1tg1 lv1 ch1tg1 lv0 ch1tg1 _8 default 0 0 0 0 0 0 0 0 cr10 (ch1 tone generator 1 control2) b7 b6 b5 b4 b3 b2 b1 b0 cr10 ch1tg1 _7 ch1tg1 _6 ch1tg1 _5 ch1tg1 _4 ch1tg1 _3 ch1tg1 _2 ch1tg1 _1 ch1tg1 _0 default 0 0 0 0 0 0 0 0 cr9-b7 to b1 ? ch1 tone generator 1 (tg1) output level setting this 7-bit field defines the output level of tg1 on ch1. the output level can be turned off or on. when turned on, the level is between ?12.1 dbm0 and +0.5 dbm0 at 0.1 dbm0 intervals as shown in table 12. the value written to this field is calculated based on the desired output level as shown in the following equation. binary data for cr9- b7 to b1 = [(output level [dbm0]) + 12.2]*10 the following is an example of how to program this field when the intended output level is ?5.8 dbm0; ex) [(output level [dbm0]) + 12.2]*10 = (-5.8 + 12.2)*10 = 64d = 1000000b bits to set in cr9-b7 to b1 = (1,0,0,0,0,0,0) table 12 tone generator 1 level setting b7 tg1lv6 b6 tg1lv5 b5 tg1lv4 b4 tg1lv3 b3 tg1lv2 b2 tg1lv1 b1 tg1lv0 level (dbm0) 0 0 0 0 0 0 0 off 0 0 0 0 0 0 1 ?12.1 0 0 0 0 0 1 0 ?12.0 0 0 0 0 0 1 1 ?11.9 0 0 0 0 1 0 0 ?11.8 : : : : : : : : 0 1 1 1 1 1 1 ?5.9 1 0 0 0 0 0 0 ?5.8 1 0 0 0 0 0 1 ?5.7 : : : : : : : : 1 1 1 1 0 1 0 0.0 1 1 1 1 0 1 1 0.1 1 1 1 1 1 0 0 0.2 1 1 1 1 1 0 1 0.3 1 1 1 1 1 1 0 0.4 1 1 1 1 1 1 1 0.5 (= 1.25 v op )
fedl7033-04 ml7033 37/52 cr9-b0, cr10-b7 to b0 ?ch1 tone generator 1 output frequency select when the ch1ring (cr11-b3) bit is cleared (?0?), these 9 bits determine the output frequency of tone generator 1 on channel 1 to a value between 300 and 3400 hz at 10hz intervals. a sample list of frequencies is shown in table 13. the value programmed into this field is calculated based on the desired frequency using the following equation. binary data for cr9-b0, cr10-b7 to b0 = (output frequency [hz])/10 the following is an example of how to progra m this field when the intended frequency is 1500 hz; ex) (output frequency [hz])/10 = 1500/10 = 150d = 10010110b bits to set in cr9-b0, cr10-b7 to b0 = (0,1,0,0,1,0,1,1,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 300 and 3400 hz. table 13 tone generator frequency setting (ch1ring bit = ? 0 ? ) cr9 cr10 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 300 30 01eh 0 0 0 0 1 1 1 1 0 310 31 01fh 0 0 0 0 1 1 1 1 1 320 32 020h 0 0 0 1 0 0 0 0 0 : : : : : : : : : : : : 400 40 028h 0 0 0 1 0 1 0 0 0 410 41 029h 0 0 0 1 0 1 0 0 1 : : : : : : : : : : : : 1000 100 064h 0 0 1 1 0 0 1 0 0 1010 101 065h 0 0 1 1 0 0 1 0 1 : : : : : : : : : : : : 2000 200 0c8h 0 1 1 0 0 1 0 0 0 : : : : : : : : : : : : 3000 300 12ch 1 0 0 1 0 1 1 0 0 : : : : : : : : : : : : 3390 339 153h 1 0 1 0 1 0 0 1 1 3400 340 154h 1 0 1 0 1 0 1 0 0
fedl7033-04 ml7033 38/52 when the ch1ring (cr11-b3) bit is set (?1?), the ch1tg1_8 (cr9-b0) bit and the ch1tg1_7 to ch1tg1_6 (cr10-b7 to b6) bits are ignored and the ch1tg1_5 to ch1tg1_0 (cr10-b5 to b0) bits are used to define the ringing tone frequency. when the ch1ring (cr11-b3) bit is set, the frequency can be set to a value between 15 hz and 50 hz at 1 hz intervals. the value programmed into this field is calculated based on the desired frequency using the following equatio n. a partial list of frequencies is shown in table 14. binary data for cr10-b5 to b0 = (output frequency [hz]) the following is an example of how to progra m this field when the intended frequency is 20hz; ex) output frequency [hz] = 20d = 010100b bits to set in cr10-b5 to b0 = (0,1,0,1,0,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 15 and 50hz. table 14 tone generator frequency setting (ch1ring bit = ?1?) cr9 cr10 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 15 15 0fh ? ? ? 0 0 1 1 1 1 16 16 10h ? ? ? 0 1 0 0 0 0 17 17 11h ? ? ? 0 1 0 0 0 1 18 18 12h ? ? ? 0 1 0 0 1 0 19 19 13h ? ? ? 0 1 0 0 1 1 20 20 14h ? ? ? 0 1 0 1 0 0 : : : : : : : : : : : : 48 48 30h ? ? ? 1 1 0 0 0 0 49 49 31h ? ? ? 1 1 0 0 0 1 50 50 32h ? ? ? 1 1 0 0 1 0
fedl7033-04 ml7033 39/52 cr11 (ringing_on and trapezoid crest factors control) b7 b6 b5 b4 b3 b2 b1 b0 cr11 ch2 ring ch2tg1 trp2 ch2tg1 trp1 ch2tg1 trp0 ch1 ring ch1tg1 trp2 ch1tg1 trp1 ch1tg1 trp0 default 0 0 0 0 0 0 0 0 b7 ? ch2 tone generator 1 (tg1) function select 0 : ch2tg1 works as a non-ringing tone generator (300 to 3400 hz) 1 : ch2tg1 works as a ringing tone generator (15 to 50 hz) the frequency and level of ch2tg1 are set by cr16 to cr17. b6 to b4 ? ch2 ringing tone waveform setting this 3-bit field determines the type of ringing tone waveform for tg1 on ch2. a sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 v and 1.375 v at 0.025 v intervals, can be selected as shown in table 15. for a definition of ?crest factor?, refer to figure 13. these bits are valid when the ch2ring (cr11-b7) bit is set. b3 ? ch1 tg1 function select 0 : ch1tg1 works as a non-ringing tone generator (300 to 3400 hz) 1 : ch1tg1 works as a ringing tone generator (15 to 50 hz) the frequency and level of ch 1tg1 are set by cr9 to cr10. b2 to b0 ? ch1 ringing tone waveform setting this 3-bit field determines the type of ringing tone waveform for tg1 on ch1. a sinusoidal waveform, or a trapezoidal waveform with a crest factor between 1.225 v and 1.375 v at 0.025 v intervals, can be selected as shown in table 15. for a definition of ?crest factor?, refer to figure 13. these bits are valid when the ch1ring (cr11-b3) bit is set. figure 13 ringing tone waveform table 15 crest factor setting b6/b2 tg1 trp2 b5/b1 tg1 trp1 b4/b0 tg1 trp0 crest factor 0 0 0 off 0 0 1 1.225 0 1 0 1.250 0 1 1 1.275 1 0 0 1.300 1 0 1 1.325 1 1 0 1.350 1 1 1 1.375 a 1 a vp 3 / 4 1 / 1 a r crestfacto ? ?
fedl7033-04 ml7033 40/52 cr12 (ch2 transmit/receive level control) b7 b6 b5 b4 b3 b2 b1 b0 cr12 lv2r3 lv2r2 lv2r1 lv2r0 lv2x3 lv2x2 lv2x1 lv2x0 default 0 0 0 0 0 0 0 0 b7 to b4 ? level setting for ch2 on its receive side this 4-bit field determines the level setting for the ch2 receive side. the settings range from 0 to ?14 dbm0 as shown in table 16. b3 to b0 ? level setting for ch2 on its transmit side this 4-bit field determines the level setting for the ch2 transmit side. the settings range from 0 to ?14 dbm0 as shown in table 16. table 16 receive and transmit level setting lv2r3/ lv2x3 lv2r2/ lv2x2 lv2r1/ lv2x1 lv2r0/ lv2x0 level (dbm0) 0 0 0 0 0.0 0 0 0 1 ?1.0 0 0 1 0 ?2.0 0 0 1 1 ?3.0 0 1 0 0 ?4.0 0 1 0 1 ?5.0 0 1 1 0 ?6.0 0 1 1 1 ?7.0 1 0 0 0 ?8.0 1 0 0 1 ?9.0 1 0 1 0 ?10.0 1 0 1 1 ?11.0 1 1 0 0 ?12.0 1 1 0 1 ?13.0 1 1 1 0 ?14.0 1 1 1 1 off
fedl7033-04 ml7033 41/52 cr13 (slic 2 control) b7 b6 b5 b4 b3 b2 b1 b0 cr13 f2_2 f1_2 f0_2 swc2 bsel2 e0_2 det2 alm2 default 0 0 0 0 0 0 - - * cr13-b1 and b0 are read-only bits. though either of ?0? or ?1? will do for these registers when a byte-wide write action is made, the written values are ignored. * the int pin which stays at logic ?0? will be released to logic ?1? when both of this control register (cr13) and slic 1 control register (cr6) are read. b7 to b5 ? operation mode setting for slic2 this 3-bit field determines the output level of the fn_2 pins. for more detail, refer to table 6. when any of these bits are cleared, the corresponding fn_2 pin outputs a logic ?0?. when any of these bits are set, the corresponding fn_2 pin outputs a logic ?1?. b4 ? uncommitted switch control for slic2 0 : switch on 1 : switch off this bit determines the output level of the swc2 pin. when this bit is cleared, the swc2 pin outputs a logic ?0?. when this bit is set, the swc2 pin outputs a logic ?1?. when the slic connected to ch annel 2 is an intersil rslic tm series device, the internal uncommitted switch of the slic, located between the sw+ and the sw- pins, can be controlled by connecting the swc2 pin directly to the corresponding input pin of the slic device. b3 ? battery mode select for slic2 0 : low battery mode 1 : high battery mode this bit determines the output level for the bsel2 pin. when this bit is cleared, the bsel2 pin outputs a logic ?0?. when this bit is set, the bsel2 pin outputs a logic ?1?. when the slic connected to ch2 is an intersil rslic tm series device, the battery mode selection of the slic is possible by connecting the bsel2 pin directly to the corresponding input pin of the slic device. b2 ? detector mode selection for slic2 this bit determines the output level of the e0_2 pin. when this bit is cleared, the e0_2 pin outputs a logic ?0?. when this bit is set, the e0_2 pin outputs a logic ?1?. when the slic connected to channel 2 is an intersil rslic tm series device, the detector mode selection of the slic is possible by connecting the e0_2 pin directly to the corresponding input pin of the slic device. th e event detected by the slic is determined by the f2_2, f1_2, f0_2 and e0_2 output pins as shown in table 6. the output level from the e0_2 pin changes 20 ? s later (hold timer) in the power-on mode with the pdn pin = logic ?1?, and 200 ns later in the power-down mode with the pdn pin = logic ?0? than a change of this bit value. refer to figure 6 for more information.
fedl7033-04 ml7033 42/52 b1 ? event detection indicator for slic2 (read-only bit) 0 : detected 1 : not detected by reading the state of this bit, the input level to the det2 pin can be determined. if this bit is cleared, the det2 pin is a logic ?0?. if this bit is set, the det2 pin is a logic ?1?. when the slic connected to ch annel 2 is an intersil rslic tm series device, an assigned event of off-hook, ring trip or ground key can be detected by connecting the det2 pin of the ml7033 directly to the corresponding output pin of the slic device. the event detected by the the slic is determined by the f2_2, f1_2, f0_2 (cr13-b7 to b5), and e0_2 (cr13-b2) bits. when a debounce timer is enabled by a setting with the det2tim3 through det2tim0 bits (cr4-b7 to b4), the det2 (cr13-b1) bit is held unchanged for a set period, even when the det2 pin changes from a logic ?1? to a logic ?0?. b0 ? thermal shutdown alarm indicator for slic2 (read-only bit) 0 : detect 1 : not detect by reading the state of this bit, the input level to the alm2 pin can be determined. if this bit is cleared, the alm2 pin is a logic ?0?. if this bit is set, the alm2 pin is a logic ?1?. when the slic connected to channel 2 is an intersil rslic tm series device, connecting the alm2 pin directly to the corresponding output pin of the slic device allows the ml7033 to know whether the slic is in the normal ope rating mode, or in a thermal shutdown state.
fedl7033-04 ml7033 43/52 cr14 (ch2 tone generator 2 control1) b7 b6 b5 b4 b3 b2 b1 b0 cr14 aout2 sel ch2tg2 tx ch2tg2 tout2 ch2tg2 lv3 ch2tg2 lv2 ch2tg2 lv1 ch2tg2 lv0 ch2tg2 _8 default 0 0 0 0 0 0 0 0 cr15 (ch2 tone generator 2 control2) b7 b6 b5 b4 b3 b2 b1 b0 cr15 ch2tg2 _7 ch2tg2 _6 ch2tg2 _5 ch2tg2 _4 ch2tg2 _3 ch2tg2 _2 ch2tg2 _1 ch2tg2 _0 default 0 0 0 0 0 0 0 0 cr14-b7 ? aout2p, aout2n output select 0 : single-ended output with the aout2p pin with the aout2n pin at high impedance. 1 : differential output with the aout2p and the aout2n pins. b6 ? ch2 tone generator output select 0 : to rx side 1 : to tx side b5 ? ch2 tone generator rx side output pin select 0 : aout2 pin 1 : tout2 pin b4 to b1 ? ch2 tg2 output level setting this 4-bit field determines the output level of tg2 on ch2. the output level ranges from ?12 to +2 dbmo as shown in table 17. table 17 tone generator 2 level setting b4 tg2lv3 b3 tg2lv2 b2 tg2lv1 b1 tg2lv0 level (dbm0) 0 0 0 0 off 0 0 0 1 ?12.0 0 0 1 0 ?11.0 0 0 1 1 ?10.0 0 1 0 0 ?9.0 0 1 0 1 ?8.0 0 1 1 0 ?7.0 0 1 1 1 ?6.0 1 0 0 0 ?5.0 1 0 0 1 ?4.0 1 0 1 0 ?3.0 1 0 1 1 ?2.0 1 1 0 0 ?1.0 1 1 0 1 0.0 1 1 1 0 +1.0 1 1 1 1 +2.0
fedl7033-04 ml7033 44/52 cr14-b0, cr15-b7 to b0 ? ch2 tg2 frequency select these 9 bits define the output frequency for tg2 on ch2. the frequency range is between 300 and 3400 hz in 10 hz intervals as shown in table 18. the output frequency is calculated using the following formula: binary data for cr14-b0, cr15-b7 to b0 = (output frequency [hz])/10 the following example shows how to progra m the output frequency when the intended frequency is 1500 hz; ex) (output frequency [hz]) / 10 = 1500/10 = 150d = 10010110b bits to set in cr14-b0, cr15-b7 to b0 = (0,1,0,0,1,0,1,1,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 300 and 3400 hz. table 18 tone generator frequency setting cr14 cr15 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 300 30 01eh 0 0 0 0 1 1 1 1 0 310 31 01fh 0 0 0 0 1 1 1 1 1 320 32 020h 0 0 0 1 0 0 0 0 0 : : : : : : : : : : : : 400 40 028h 0 0 0 1 0 1 0 0 0 410 41 029h 0 0 0 1 0 1 0 0 1 : : : : : : : : : : : : 1000 100 064h 0 0 1 1 0 0 1 0 0 1010 101 065h 0 0 1 1 0 0 1 0 1 : : : : : : : : : : : : 2000 200 0c8h 0 1 1 0 0 1 0 0 0 : : : : : : : : : : : : 3000 300 12ch 1 0 0 1 0 1 1 0 0 : : : : : : : : : : : : 3390 339 153h 1 0 1 0 1 0 0 1 1 3400 340 154h 1 0 1 0 1 0 1 0 0
fedl7033-04 ml7033 45/52 cr16 (ch2 tone generator 1 control1) b7 b6 b5 b4 b3 b2 b1 b0 cr16 ch2tg1 lv6 ch2tg1 lv5 ch2tg1 lv4 ch2tg1 lv3 ch2tg1 lv2 ch2tg1 lv1 ch2tg1 lv0 ch2tg1 _8 default 0 0 0 0 0 0 0 0 cr17 (ch2 tone generator 1 control2) b7 b6 b5 b4 b3 b2 b1 b0 cr17 ch2tg1 _7 ch2tg1 _6 ch2tg1 _5 ch2tg1 _4 ch2tg1 _3 ch2tg1 _2 ch2tg1 _1 ch2tg1 _0 default 0 0 0 0 0 0 0 0 cr16-b7 to b1 ? ch2 tg1 output level setting this 7-bit field defines the output level of tone generator 1 on channel 2. the output level ranges from ?12.1 to +0.5 dbm0 in 0.1 dbm0 intervals as shown in table 19. a value of 0 in this field disables the tone generator. the output level is calculated using the following formula. binary data for cr16- b7 to b1 = [(output level [dbm0]) + 12.2]*10 the following example shows how to program this field when the intended output level is ?5.8 dbm0; ex) [(output level [dbm0]) + 12.2]*10 = (?5.8 + 12.2)*10 = 64d = 1000000b bits to set in cr9-b7 to b1 = (1,0,0,0,0,0,0) table 19 tone generator 1 level setting b7 tg1lv6 b6 tg1lv5 b5 tg1lv4 b4 tg1lv3 b3 tg1lv2 b2 tg1lv1 b1 tg1lv0 level (dbm0) 0 0 0 0 0 0 0 off 0 0 0 0 0 0 1 ?12.1 0 0 0 0 0 1 0 ?12.0 0 0 0 0 0 1 1 ?11.9 0 0 0 0 1 0 0 ?11.8 : : : : : : : : 0 1 1 1 1 1 1 ?5.9 1 0 0 0 0 0 0 ?5.8 1 0 0 0 0 0 1 ?5.7 : : : : : : : : 1 1 1 1 0 1 0 0.0 1 1 1 1 0 1 1 0.1 1 1 1 1 1 0 0 0.2 1 1 1 1 1 0 1 0.3 1 1 1 1 1 1 0 0.4 1 1 1 1 1 1 1 0.5 (= 1.25 v op )
fedl7033-04 ml7033 46/52 cr16-b0, cr17-b7 to b0 ? ch2 tg1 frequency select when the ch2ring (cr11-b7) bit is cleared, th is 9-bit field is valid and determines the output frequency from tone generator 1 on channel 2. the frequency range is between 300 and 3400 hz at 10 hz intervals as shown in table 20. the output level is calculated using the following formula. binary data for cr16-b0, cr17-b7 to b0 = (output frequency [hz])/10 the following is an example of how to program this register field when the intended frequency is 1500 hz; ex) (output frequency [hz]) / 10 = 1500/10 = 150d = 10010110b bits to set in cr16-b0, cr17-b7 to b0 = (0,1,0,0,1,0,1,1,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 300 and 3400 hz. table 20 tone generator frequency setting (ch2ring bit = ?0?) cr16 cr17 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 300 30 01eh 0 0 0 0 1 1 1 1 0 310 31 01fh 0 0 0 0 1 1 1 1 1 320 32 020h 0 0 0 1 0 0 0 0 0 : : : : : : : : : : : : 400 40 028h 0 0 0 1 0 1 0 0 0 410 41 029h 0 0 0 1 0 1 0 0 1 : : : : : : : : : : : : 1000 100 064h 0 0 1 1 0 0 1 0 0 1010 101 065h 0 0 1 1 0 0 1 0 1 : : : : : : : : : : : : 2000 200 0c8h 0 1 1 0 0 1 0 0 0 : : : : : : : : : : : : 3000 300 12ch 1 0 0 1 0 1 1 0 0 : : : : : : : : : : : : 3390 339 153h 1 0 1 0 1 0 0 1 1 3400 340 154h 1 0 1 0 1 0 1 0 0 when the ch2ring (cr11-b7) bit is set, the setting of the ch2tg1_8 (cr16-b0) bit and the ch2tg1_7 to ch2tg1_6 (cr16-b7 to b6) bits are ignored, and the ch2tg1_5 to ch2tg1_0 (cr16-b5 to b0) field defines the ringing tone frequency. when the ch2ring (cr11-b7) bit is set, the frequency range is between 15 and 50 at 1 hz intervals as shown in table 21. the output frequency is calculated using the following formula. binary data for cr17-b5 to b0 = (output frequency [hz])
fedl7033-04 ml7033 47/52 the following example shows ho w to program this register field when the intended frequency is 20 hz; ex) output frequency [hz] = 20d = 010100b bits to set in cr17-b5 to b0 = (0,1,0,1,0,0) note that the operations are no t guaranteed when these bits define a frequency out of a band between 15 and 50 hz. table 21 tone generator frequency setting (ch2ring bit = ?1?) cr16 cr17 frequency (hz) decimal hex b0 b7 b6 b5 b4 b3 b2 b1 b0 15 15 0fh ? ? ? 0 0 1 1 1 1 16 16 10h ? ? ? 0 1 0 0 0 0 17 17 11h ? ? ? 0 1 0 0 0 1 18 18 12h ? ? ? 0 1 0 0 1 0 19 19 13h ? ? ? 0 1 0 0 1 1 20 20 14h ? ? ? 0 1 0 1 0 0 : : : : : : : : : : : : 48 48 30h ? ? ? 1 1 0 0 0 0 49 49 31h ? ? ? 1 1 0 0 0 1 50 50 32h ? ? ? 1 1 0 0 1 0
fedl7033-04 ml7033 48/52 cr18 (test control) b7 b6 b5 b4 b3 b2 b1 b0 cr18 ch2 loop1 ch2 loop0 ch1 loop1 ch1 loop0 test3 test2 test1 test0 default 0 0 0 0 0 0 0 0 b7, b6 ? ch2 loop-back test mode select (b7, b6): (0, 0) = loop-back off (0, 1) = loop-back off (1, 0) = channel 2 digital loop-back test. pcm data output on the pcmout pin during normal operation is internally looped ba ck through the receive path via the pcmin pin. in digital loop-back test mode, input data on pcmin pin is ignored, but pcm data continues to be output on the pcmout pin. (1, 1) = channel 2 analog loop-back test. analog signals output on the aout2p pin (or the aout2p and aout2n pins) are internally looped back to the transmit path behind a built-in feedback amplifier located after the ain2p, ain2n and gsx2 pins. in this mode, the ain2p and ain2n input pins are ignored. however, analog signals continue to be output on the aout2p pin (or the aout2p and the aout2n pins). a loop-back test is functional only if xsync and rsync are from the same clock source. b5, b4 ? ch1 loop-back test mode select (b5, b4): (0, 0) = loop-back off (0, 1) = loop-back off (1, 0) = channel 1 digital loop-back test. pcm data is output on the pcmout pin in normal operation is internally looped ba ck through the receive path via the pcmin pin. in loop-back test mode, input data on pcmin pin is ignored. however, pcm data can be output on the pcmout pin. (1, 1) = channel 1 analog loop-back test. analog signals output on the aout1p pin (or from the aout1p and the aout1n pins) are internally looped back to the transmit path via a built-in feedback amp lifier located after the ain1p, ain1n and gsx1 pins. in this mode, the ain1p and ain1n input pins are ignored. however, analog signals can be outp ut from the aout1p pin (or from the aout1p and the aout1n pins). a loop-back test is functional if xsync and rsync are from the same clock source. b3 to b0 ? lsi test registers for an lsi manufacturer the default alternation is prohibited. when a write action is executed for cr18, set all of these bits to ?0?.
fedl7033-04 ml7033 49/52 cr19 (lsi manufacturer?s test control) b7 b6 b5 b4 b3 b2 b1 b0 cr19 test11 test10 test9 test8 test7 test6 test5 test4 default 0 0 0 0 0 0 0 0 b7 to b0 ? lsi test registers for an lsi manufacturer for manufacturing use only. both reads and writes to this register are prohibited.
fedl7033-04 ml7033 50/52 package dimensions notes for mounting the surface mount type package the surface mount type packages ar e very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform refl ow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package co de and desired mounting conditions (reflow method, temperature and times). qfp64-p-1414-0.80-bk mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5 m) package weight (g) 0.87 typ. 5 rev. no./last revised 6/feb. 23, 2001 (unit: mm)
fedl7033-04 ml7033 51/52 revision history page document no. date previous edition current edition description fedl7033-02 dec. 2001 ? ? final edition 2 12 12 added t 12 corrected values of serial port i/o setting time 16 16 added t 12 corrected figure 5 serial interface fedl7033-03 jun. 8, 2007 ? 51 added ?revision history? fedl7033-04 oct. 13, 2011 ? ? company name change
fedl7033-04 ml7033 52/52 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants an d any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or othe r rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatso ever for any dispute arising from the use of such technical information. the products specified in this documen t are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe desi gns. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a me dical instrument, transpor tation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety devi ce). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, pleas e contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 lapis semiconductor co., ltd.

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